In recent years, the performance (functionality) of electronic devices using a semiconductor device (package) having a semiconductor element (chip) mounted therein has been increasing. Accordingly, there are demands for an increase in density in the mounting of semiconductor chips on a wiring board in such a semiconductor device, and a reduction in size (particularly, in thickness) and footprint of the board having the chips mounted therein. For this reason, wiring boards having semiconductor elements embedded and mounted therein have been proposed, and various structures and methods for such wiring boards have been proposed as well.
As a form of the aforementioned wiring boards, there is a wiring board called a bumpless mounting board. The bumpless mounting board uses a substrate in which diced semiconductor elements are embedded and sealed (fixed) by resin (such as an epoxy-based resin or phenol resin containing filler) while electrode pads (terminals) of each semiconductor element are exposed on the surface thereof. In addition, wiring layers are stacked on the resin used to seal the semiconductor element and also on the semiconductor element.
In the structure (process) described above, the semiconductor element and the wiring layers can be connected to each other in the course of the process of stacking layers on the substrate with copper plating or the like. Accordingly, no solder connection (bumps) between the semiconductor element and the wiring board is required in this case, the solder connection required in flip-chip connection performed when a general semiconductor element mounted board (wiring board on which a semiconductor element is surface-mounted) is formed. Thus, such a process allows formation of a semiconductor package thinner than a semiconductor package using an existing thin-core substrate or coreless substrate requiring flip-chip connection. In addition, the inductance of the semiconductor element mounted wiring board is reduced in this case because of the thickness reduction. Thus, such a board is very effective in terms of the power supply characteristics.
In addition, a package with a package-on-package (POP) structure formed by stacking such bumpless mounting boards (packages) one on top of another in the height direction of the boards is expected to be thinner than that with a POP structure of the current technology (structure in which semiconductor element mounted boards requiring flip-chip connection are stacked one on top of another).
As an example of techniques relating to the aforementioned conventional art, there is known a technique used in a small electronic package in which a small electronic component (die) having an active surface and a side surface is sealed. With this technique, a sealing member having a surface substantially in parallel with the active surface of the die is arranged adjacent to the side surface of the die (International Publication Pamphlet No. WO 02/15266).
As another known technique, there is a technique used in a small electronic board in which a small electronic component (die) is sealed. With this technique, the die is arranged at an opening portion of a board core, and an area of the opening portion, which is not occupied by the die, is filled with a sealing member (International Publication Pamphlet No. WO 02/33751).
As described above, in the structure (process) of the conventional semiconductor element mounted board, the semiconductor element sealed by resin is used as the base substrate, and the wiring layers are sequentially stacked on the base substrate (on the resin used for the sealing and semiconductor element). Accordingly, once a defect occurs during formation of the wiring layers, it results in a waste of the semiconductor element sealed by resin. For this reason, there has been a problem that such a situation leads to a reduction in the fabrication yield in volume production.